1. Field of the Invention
The present invention relates to a semiconductor storage device having a precharge/equalize function of charging bit lines to a predetermined equal potential before reading of information from a memory cell to bit lines, such as a static semiconductor storage device, a dynamic semiconductor storage device, or the like. The present invention also relates to an information apparatus using such a semiconductor storage device.
2. Description of the Related Art
In recent years, in semiconductor storage devices, an increase of storage capacity, a decrease of device size, and an increase of operational speed have been energetically promoted. This also applies to a static semiconductor storage device. As a method for increasing an operational speed, a bit line equalizing method is employed for a static semiconductor storage device having a pair of complementary bit lines BIT/BIT#. In this method, a selected pair of complementary bit lines BIT/BIT# are precharged before a data read operation, to an equal potential, for example, Vcc/2 when the power supply voltage is Vcc. At the time when the data read operation is started in response to this equalizing operation, a very small difference is caused in an output of a memory cell with respect to the precharged potential. This potential difference is amplified by a sense amplifier, whereby data stored in the memory cell is read out.
Thus, even when the very small potential difference between the pair of complementary bit lines BIT/BIT# is amplified for data reading, it is not necessary to make a full swing of (i.e., it is not necessary to largely change) the potentials of the pair of complementary bit lines BIT/BIT# up to the power supply potential or ground potential. As a result, the speed of the data read operation is increased.
Generally, in a bit line equalizing operation, bit lines are precharged to an intermediate potential which is lower than the power supply voltage Vcc, for example, precharged to Vcc/2. Thus, a semiconductor storage device which performs the equalizing operation must incorporate a voltage decreasing circuit for decreasing the potentials of the bit lines to Vcc/2.
A circuit structure of a conventional, commonly-employed static semiconductor storage device, which incorporates an equalizing circuit for performing the above equalizing operation, is shown in FIG. 8.
In FIG. 8, a conventional static semiconductor storage device 10 includes: an internal voltage decreasing circuit 1; a load transistor 2; a memory cell array 3 formed by a plurality of memory cells; a row decoder 4 for selecting among word lines; a column switch circuit 5 for controlling the on/off state of each bit line; a column decoder 6 for selecting among bit lines; a sense amplifier 7 for sensing memory data; an equalizing circuit 8 provided at one side of the memory cell array 3; and an equalizing circuit 9 provided at the other side of the memory cell array 3.
An input terminal of the internal voltage decreasing circuit 1 is connected to the power supply voltage Vcc. An output of the internal voltage decreasing circuit 1, Vccin, is supplied to the row decoder 4 and the equalizing circuits 8 and 9 (hereinafter, referred to as “EQ circuits 8 and 9”), and also supplied to the memory cell array 3 via the load transistor 2 and pairs of complementary bit lines BL1/BL1# through BLn/BLn#. Further, the output Vccin of the internal voltage decreasing circuit 1 is supplied via the EQ circuit 9 to the pair of complementary bit lines BL1/BL1# through BLn/BLn#, and on the other hand, is supplied via the EQ circuit 8 to pairs of complementary node lines SEN1/SEN1# through SENn/SENn#.
In order to prevent a pair of complementary bit lines from being placed in a floating state, a very small amount of electric current is always allowed to flow through the load transistor 2. As shown in FIG. 9, the load transistor 2 includes a plurality of PMOS transistors P1 and P2. In order to constantly place the PMOS transistors P1 and P2 in a conductive state, gates of the PMOS transistors P1 and P2 are connected to the ground potential; sources of the PMOS transistors P1 and P2 are connected to the output of the internal voltage decreasing circuit 1; and the drains of the PMOS transistors P1 and P2 are connected to the pairs of complementary bit lines BL1/BL1# through BLn/BLn# and also connected through these bit lines to the EQ circuit 9.
The memory cell array 3 includes a plurality of memory cells 3a. The plurality of memory cells 3a are provided at intersections of the pairs of complementary bit lines BL1/BL1# through BLn/BLn# and word lines WL1 through WLn in a matrix pattern.
The row decoder 4 sequentially selects among the word lines WL1 through WLn based on a result of decoding of an address.
The column switch circuit 5 is provided between a pair of complementary bit lines BLi/BLi# and a pair of complementary node lines SENi/SENi# (where i denotes a natural number selected from 1 to n). The column switch circuit 5 is formed by transfer circuits 5a and 5b. The transfer circuits 5a and 5b control the on/off state of the connection between the pair of complementary bit lines BLi/BLi# and the pair of complementary node lines SENi/SENi#. Specifically, as shown in FIG. 10, the transfer circuit 5a includes a PMOS transistor P6 and an NMOS transistor N3. In response to a bit line selection signal from the column decoder 6, the PMOS transistor P6 and the NMOS transistor N3 are both turned on/off, whereby the pairs of complementary bit lines BL1/BL1# through BLn/BLn# are connected to or disconnected from the sense amplifier 7. In this way, the transfer circuit 5a selects among the bit lines.
The column decoder 6 drives and controls each transfer circuit of the column switch circuit 5 based on a result of decoding of an address.
The sense amplifier 7 amplifies a potential variation generated in an output of a memory cell 3a and detects the amplified potential variation, thereby reading information from the memory cell 3a. 
The EQ circuit 8 has a function of precharging the pair of complementary bit lines BLi/BLi# to an equal potential and of equalizing the potentials of the pair of complementary bit lines BLi/BLi#. An output terminal of the EQ circuit 8 and an output terminal of the load transistor 2 is connected to the pair of complementary bit lines BLi/BLi# in parallel.
The EQ circuit 9 is connected between the column switch circuit 5 and the sense amplifier 7. The EQ circuit 9 has a function of precharging and equalizing the pair of complementary node lines SENi/SENi# provided at the side of the sense amplifier 7. An example of a circuitry structure of the EQ circuit 9 is shown in FIG. 11.
As shown in FIG. 11, the EQ circuit 9 includes P-type MOS transistors P3 to P5. Sources and back gates of the P-type MOS transistors P3 and P4 are connected to the output terminal Vccin of the internal voltage decreasing circuit 1. A drain of the P-type MOS transistor P3 is connected to a node line SENi which is connected to an output terminal of the column switch circuit 5. A drain of the P-type MOS transistor P4 is connected to a node line SENi# which is connected to another output terminal of the column switch circuit 5. The pair of complementary node lines SENi/SENi# are connected through the column switch circuit 5 to the pair of complementary bit lines BLi/BLi#, respectively. Further, in order to equalize the pair of complementary node lines SENi/SENi#, a source and a drain of the P-type MOS transistor P5 are connected between the complementary node lines SENi/SENi#. A back gate of the P-type MOS transistor P5 is connected to the output terminal Vccin of the internal voltage decreasing circuit 1. Furthermore, an equalizing signal EQ# output from an internal timing circuit (not shown in FIG. 11) is supplied to the gates of the P-type MOS transistors P3 to P5. During a period when the equalizing signal EQ# is at a low level, the P-type MOS transistors P3 to P5 are all conducted. As a result, the pair of the complementary node lines SENi/SENi# are precharged by the P-type MOS transistors P3 and P4 to a voltage level of the output Vccin (e.g., Vcc/2), and the voltages of the pair of the complementary node lines SENi/SENi# are equalized by the P-type MOS transistor P5.
In the above operation, lines which have to be precharged and equalized in order to read information from a selected memory cell 3a are the pair of complementary bit lines BL1/BL1# through BLn/BLn#, and the pair of the complementary node lines SENi/SENi# which are selected by the column decoder 6 and connected to the transfer circuits 5a and 5b of the column switch circuit 5. In the conventional example shown in FIG. 8, these lines are precharged and equalized only by the output Vccin of the internal voltage decreasing circuit 1.
Further, a similar technique of increasing an operational speed of a storage device using an internal voltage decreasing circuit, which generates a voltage lower than the power supply voltage, is proposed in Japanese Laid-Open Publication No. 4-252497, entitled “Nonvolatile Semiconductor Storage Device”. Referring to FIG. 12, this nonvolatile semiconductor storage device includes an internal voltage decreasing circuit 1 which generates a voltage lower than the power supply voltage. The internal voltage decreasing circuit 1 applies a low voltage to a load transistor 2 which is connected to a sense amplifier 7. The sense amplifier 7 is used to detect a variation in the potentials of the bit lines BL1, BL1#, . . . , BLn, and BLn#, which are connected to the load transistor 2, whereby information is read from a memory cell. With such an arrangement, the sensitivity of a read current from a memory cell is increased, whereby a non volatile semiconductor storage device with an increased access speed can be obtained.
Furthermore, another example of a semiconductor storage device incorporating an internal voltage decreasing circuit, which is illustrated in FIGS. 13 and 14, is proposed in Japanese Laid-Open Publication No. 8-69693, entitled “Static semiconductor Storage Device”.
Referring to FIG. 13, this static semiconductor storage device uses an internal voltage decreasing circuit 1 to decrease an externally supplied power supply voltage Vcc so as to output a potential lower than the power supply voltage Vcc to a peripheral circuit (s). As a result, the externally supplied power supply voltage Vcc is directly applied to a static memory cell, so that the operational voltage of a memory cell array 3 is relatively increased. Thus, even when the amount of consumed electric power is small, an ON-current of a transistor in a memory cell appears to be increased. As a result, a static semiconductor storage device, where the stability in a memory cell read operation is increased, can be obtained.
Furthermore, in a static semiconductor storage device shown in FIG. 14, an output of an internal voltage decreasing circuit 1, i.e., a potential lower than the power supply voltage, is applied to a peripheral circuit section. Moreover, when data is read from a static memory cell array 3, a potential higher than the power supply potential Vcc is applied by an internal voltage increasing circuit 1A to the static memory cell array 3. In such an arrangement, an operational voltage of the memory cell array 3 is further increased only during the read operation, and an ON-current of a transistor in a memory cell appears to be increased. As a result, a static semiconductor storage device, where the stability in a memory cell read operation is increased even though the amount of consumed electric power is small, can be obtained.
In the above-described conventional structure, a low voltage decreased by the internal voltage decreasing circuit 1 is applied to the pairs of complementary bit lines BL1/BL1# through BLn/BLn#, and a potential variation generated in the pairs of complementary bit lines BL1/BL1# through BLn/BLn# due to an output of the memory cell 3a is detected using the sense amplifier 7, whereby information is read from the memory cell 3a. In the case of such a structure, the internal voltage decreasing circuit 1 must have a capacity for providing a voltage and electric current at a level sufficient for precharging the pairs of complementary bit lines BL1/BL1# through BLn/BLn#, and a capacity for securing a stable operation of the sense amplifier 7. Moreover, in a precharge period, a large amount of electric current is allowed to momentarily flow for the purpose of precharging a pair of complementary bit lines, and accordingly, the voltage is momentarily decreased. A commonly employed measure for preventing such a decrease in voltage is connecting an element having a capacitance, such as a capacitor, to an output terminal of the internal voltage decreasing circuit 1 which functions as a power supply. Thus, in order to secure stability in an operation which is performed in the presence of a large electric current load, such as a precharge operation, it is necessary to provide a sufficiently large capacitive element. However, in order to secure a large capacitance in such a capacitive element, a large device area (chip area) must be provided.
In the conventional structure shown in FIG. 8, in an operation of reading information from a selected memory cell 3a, correct information cannot be read out before precharging and equalizing of the pair of the complementary node lines SENi/SENi#, which are connected to the sense amplifier 7 via the column switch 5 selected by the column decoder 6, are completed. Further, this entire operation is performed using a voltage and electric current supplied from the internal voltage decreasing circuit 1. Thus, the voltage/current driving ability of the internal voltage decreasing circuit 1 adversely influences the time required for the precharging and equalizing operations, i.e., an increase in the speed of a data read operation. Therefore, as a driving ability of the internal voltage decreasing circuit 1 is decreased, the speed of reading data from the selected memory cell 3a is decreased. In view of such a correlation, in order to increase the data read speed, the circuit size of the internal voltage decreasing circuit 1 must be necessarily increased. These problems are especially significant in consideration of a decrease in the power supply voltage which has been achieved in recent years.